View CXP85452S_4890443.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

description the cxp85452/85460 are a highly integrated micro- computers composed of a 8-bit cpu, rom, ram, and i/o ports. these chips feature many other high- performance circuits in a single-chip cmos design, including an a/d converter, serial interface, timer/counter, time-base timer, on-screen display function, i 2 c bus interface, pwm output, remote control reception circuit, hsync counter, and watchdog timer. futhermore, the cxp85452/85460 series provides power-on reset and sleep functions which enable to lower power consumption. features a wide instruction set (213 instructions) which covers various types of data ?16-bit operation/multiplication and division/boolean bit operation instructions minimum instruction cycle 0.5s at 8mhz incorporated rom capacity 52k bytes (cxp85452) 60k bytes (cxp85460) incorporated ram capacity 960 bytes peripheral functions ?a/d converter 8-bit, 4-channel successive approximation method (conversion time of 20s at 8mhz) ?serial interface 8-bit clock sync type, 1 channel ?timer 8-bit timer 8-bit timer/counter 19-bit time-base timer ?on screen display (osd) function 12 18 dots, 384 character types, 15 character colors, 12lines of 32 characters, black frame output/half blanking, shadow, background color on full screen/half blanking, double scanning, jitter elimination circuit ?i 2 c bus interface ?pwm output 14 bits, 1 channel 8 bits, 8 channels ?remote control reception circuit 8-bit pulse measurement circuit, 6-state fifo ?hsync counter 2 channels ?watchdog timer interruption 13 factors, 13 vectors, multi-interruption possible standby mode sleep package 64-pin plastic sdip/qfp piggyback/evaluator cxp85400 64-pin ceramic psdip/pqfp cxp85490 64-pin ceramic psdip (accommodates custom font) purchase of sony's i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specifications as defined by philips. ?1 cxp85452/85460 e94323b86 cmos 8-bit single chip microcomputer sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 64 pin sdip (piastic) 64 pin qfp (piastic) structure silicon gate cmos ic
? 2 cxp85452/85460 o n s c r e e n d i s p l a y s e r i a l i n t e r f a c e u n i t 8 b i t t i m e r / c o u n t e r 0 r e m o c o n f i f o h s y n c c o u n t e r 0 h s y n c c o u n t e r 1 a / d c o n v e r t e r i 2 c b u s i n t e r f a c e u n i t w a t c h d o g t i m e r 1 4 b i t p w m 8 b i t p w m 8 c h c l o c k g e n e r a t o r / s y s t e m c o n t r o l r a m 9 6 0 b y t e s s p c 7 0 0 c p u c o r e r o m 5 2 k / 6 0 k p r e s c a l e r / t i m e b a s e t i m e r p o r t a p o r t b p o r t c p o r t d p o r t e p o r t f 2 2 v s s v d d m p x t a l e x t a l r s t i n t 2 i n t 1 i n t 0 p w m 0 t o p w m 7 i n t e r r u p t c o n t r o l l e r p w m p a 0 t o p a 7 p b 0 t o p b 7 p c 0 t o p c 7 p d 0 t o p d 7 p e 0 t o p e 5 p e 6 t o p e 7 p f 0 t o p f 7 x l c e x l c r g b i y s y m h s y n c v s y n c s i s o s c k e c t o r m c h s 0 h s 1 a n 0 t o a n 3 s c l 0 s c l 1 s d a 0 s d a 1 8 b i t t i m e r 1 block diagram
? 3 cxp85452/85460 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 3 6 4 6 1 6 2 h s y n c / p a 7 v s y n c / p a 6 p a 5 p a 4 p a 3 p a 2 p a 1 p a 0 p b 7 p b 6 p b 5 p b 4 p b 3 p b 2 p b 1 p b 0 p c 7 p c 6 p c 5 p c 4 p c 3 p c 2 p c 1 p c 0 e c / p d 7 r m c / p d 6 h s 1 / p d 5 h s 0 / p d 4 s i / p d 3 s o / p d 2 s c k / p d 1 v s s v d d n c v s s m p p f 0 / p w m 0 p f 1 / p w m 1 p f 2 / p w m 2 p f 3 / p w m 3 p f 4 / p w m 4 / s c l 0 p f 5 / p w m 5 / s c l 1 p f 6 / p w m 6 / s d a 0 p f 7 / p w m 7 / s d a 1 y m y s i b g r e x l c x l c p e 0 / i n t 0 p e 1 / i n t 1 a n 0 / p e 2 a n 1 / p e 3 a n 2 / p e 4 a n 3 / p e 5 p e 6 / p w m p e 7 / t o r s t e x t a l x t a l p d 0 / i n t 2 pin assignment (top view) 64-pin sdip note) 1. nc (pin 63) is always connected to v dd . 2. vss (pins 32 and 62) are both connected to gnd. 3. mp (pin 61) is always connected to gnd.
? 4 cxp85452/85460 note) 1. nc (pin 56) is always connected to v dd . 2. vss (pins 26 and 58) are both connected to gnd. 3. mp (pin 55) is always connected to gnd. pin assignment (top view) 64-pin qfp p a 1 p a 0 p b 7 p b 6 p b 5 p b 4 p b 3 p b 2 p b 1 p b 0 p c 7 p c 6 p c 5 p c 4 p c 3 p c 2 p c 1 p c 0 e c / p d 7 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 1 p f 3 / p w m 3 p f 4 / p w m 4 / s c l 0 p f 5 / p w m 5 / s c l 1 p f 6 / p w m 6 / s d a 0 p f 7 / p w m 7 / s d a 1 y m y s i b g r e x l c x l c p e 0 / i n t 0 p e 1 / i n t 1 a n 0 / p e 2 a n 1 / p e 3 a n 2 / p e 4 a n 3 / p e 5 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 p a 2 p a 3 p a 4 p a 5 p a 6 / v s y n c p a 7 / h s y n c v s s v d d n c m p p f 0 / p w m 0 p f 1 / p w m 1 p f 2 / p w m 2 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 3 6 4 6 1 6 2 r m c / p d 6 h s 1 / p d 5 h s 0 / p d 4 s i / p d 3 s o / p d 2 s c k / p d 1 v s s i n t 2 / p d 0 x t a l e x t a l r s t t o / p e 7 p w m / p e 6 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2
(port a) 8-bit i/o port. i/o can be set in a unit of single bits. (8 pins) (port b) 8-bit i/o port. i/o can be set in a unit of single bits. (8 pins) (port c) 8-bit i/o port. i/o can be set in a unit of single bits. (8 pins) (port d) 8-bit i/o port. i/o can be set in a unit of single bits. 12ma sink current drive possible. (8 pins) (port e) 8-bit port. lower 6 bits are for inputs; upper 2 bits are for outputs. (8 pins) (port f) 8-bit output port. large current (12ma) n-ch open drain output. lower 4 bits are mid-voltage drive (12v); upper 4 bits are 5v drive. (8 pins) osd display 6-bit output pin. (6 pins) ? 5 cxp85452/85460 pin description symbol pa0 to pa5 pa6/vsync pa7/hsync pb0 to pb7 pc0 to pc7 pd0/int2 pd1/sck pd2/so pd3/si pd4/hs0 pd5/hs1 pd6/rmc pd7/ec pe0/int0 pe1/int1 pe2/an0 to pe5/an3 pe6/pwm pe7/to pf0/pwm0 to pf3/pwm3 pf4/pwm4/ scl0 pf5/pwm5/ scl1 pf6/pwm6/ sda0 pf7/pwm7/ sda1 r, g, b, i, ys, ym i/o i/o/input i/o/input i/o i/o i/o/input i/o/i/o i/o/output i/o/input i/o/input i/o/input i/o/input i/o/input input/input input/input output/output output/output output/output output/output/ i/o output/output/ i/o output i/o description osd display vertical synchronization signal input pin. osd display horizontal synchronization signal input pin. input pin for external interruption request. active when falling edge. serial clock i/o pin. serial data output pin. serial data input pin. hsync counter (ch0) input pin. hsync counter (ch1) input pin. remote control reception circuit input pin. external event input pin for timer/counter. input pin for external interruption request. active when falling edge. (2 pins) analog input pin for a/d converter. (4 pins) 14-bit pwm output pin. (cmos output) timer/counter rectangular wave output pin. 8-bit pwm output pin. (8 pins) i 2 c bus interface transfer clock i/o pin. (2 pins) i 2 c bus interface transfer data i/o pin. (2 pins)
? 6 cxp85452/85460 symbol exlc xlc extal xtal rst mp nc v dd vss input output input output i/o input osd display clock oscillation i/o pin. oscillation frequency is determined by the external l and c. crystal connection pin for system clock oscillation. when using an external clock, input to extal pin and leave xtal pin open. system reset pin for active at low level. this pin becomes i/o pin, and outputs low level at the power on with power-on reset function executed. (mask option) test mode input pin. always connect to gnd. nc. under normal operation, connect to v dd . positive supply voltage pin. gnd. both vss pins should be connected to common gnd. i/o description
? 7 cxp85452/85460 d a t a b u s r d ( p o r t s a , b , c ) a a a a i p a a a a i n p u t p r o t e c t i o n c i r c u i t a a a a a a a a a a p o r t s a , b , c d a t a a a a a a a a a a a p o r t s a , b , c d i r e c t i o n 0 w h e n r e s e t d a t a b u s r d ( p o r t a ) a a a a i p a a a a s c h m i t t i n p u t a a a a a a a a p o r t a d i r e c t i o n a a a a a a a a p o r t a d a t a a a a a a a a a i n p u t m u l t i p l e x e r v s y n c h s y n c 0 w h e n r e s e t 0 w h e n r e s e t d a t a b u s r d ( p o r t d ) a a a a i p a a a a a a a a a a a a p o r t d d i r e c t i o n a a a a a a a a p o r t d d a t a i n t 2 , s i , h s 0 , h s 1 , r m c , e c s c h m i t t i n p u t 0 w h e n r e s e t * * l a r g e c u r r e n t 1 2 m a input/output circuit formats for pins port a port b port c port a port d 22 pins 2 pins 6 pins hi-z hi-z hi-z pin when reset circuit format pa0 to pa5 pb0 to pb7 pc0 to pc7 pa6/vsync pa7/hsync pd0/int2 pd3/si pd4/hs0 pd5/hs1 pd6/rmc pd7/ec
? 8 cxp85452/85460 d a t a b u s r d ( p o r t d ) a a a a i p a a a a a a a a p o r t d d i r e c t i o n a a a a p o r t d d a t a s c h m i t t i n p u t s c k o n l y s c k o r s o o u t p u t e n a b l e 0 w h e n r e s e t * * l a r g e c u r r e n t 1 2 m a a a a a a a i p r d ( p o r t e ) d a t a b u s s c h m i t t i n p u t ( i n t e r r u p t c i r c u i t ) i n p u t m u l t i p l e x e r t o a / d c o n v e r t e r r d ( p o r t e ) d a t a b u s a a a a a a i p a a a a a a a a a a p o r t e f u n c t i o n s e l e c t i o n 0 w h e n r e s e t t o , p w m a a a a a a a a a a p o r t e f u n c t i o n s e l e c t i o n a a a a a a a a a a a a a a p o r t e d a t a 1 w h e n r e s e t 1 w h e n r e s e t port d port e 2 pins 2 pins 4 pins 2 pins pin when reset circuit format pe0/int0 pe1/int1 port e port e hi-z hi-z hi-z high level pe2/an0 to pe5/an3 pd1/sck pd2/so pe6/pwm pe7/to
? 9 cxp85452/85460 s c l , s d a a a a a a a a a a a p o r t f f u n c t i o n s e l e c t i o n a a a a a a a a a a a a p o r t f d a t a p w m i 2 c o u t p u t e n a b l e a i p s c h m i t t i n p u t s c l , s d a ( i 2 c c i r c u i t ) t o i n t e r n a l i 2 c p i n s b u s s w * * l a r g e c u r r e n t 1 2 m a 1 w h e n r e s e t 0 w h e n r e s e t p w m a a a a a a a a a a p o r t f s e l e c t i o n a a a a a a a a a a a a p o r t f d a t a * * 1 2 v v o l t a g e d r i v e l a r g e c u r r e n t 1 2 m a 1 w h e n r e s e t 0 w h e n r e s e t port f port f 4 pins 4 pins 6 pins 2 pins pin when reset circuit format pf4/pwm4/ scl0 pf5/pwm5/ scl1 pf6/pwm6/ sda0 pf7/pwm7/ sda1 hi-z hi-z hi-z oscillation halted r g b i ys ym pf0/pwm0 to pf3/pwm3 exlc xlc a a a a r , g , b , i , y s , y m w r i t i n g d a t a t o o u t p u t p o l a r i t y r e g i s t e r b r i n g s o u t p u t t o a c t i v e a a a a a a a a o u t p u t p o l a r i t y 0 w h e n r e s e t o s c i l l a t o r c o n t r o l a a a a e x l c a a a a a a i p o s d d i s p l a y c l o c k a a a a i p x l c
? 10 cxp85452/85460 2 pins 1 pin pin when reset circuit format rst oscillation low level extal xtal a a a a a a i p a a a a e x t a l x t a l s h o w s t h e c i r c u i t c o m p o s i t i o n d u r i n g o s c i l l a t i o n . f e e d b a c k r e s i s t o r i s r e m o v e d d u r i n g s t o p . ( t h i s d e v i c e d o e s n o t e n t e r t h e s t o p m o d e . ) a a a a s c h m i t t i n p u t p u l l - u p r e s i s t o r f r o m p o w e r - o n r e s e t c i r c u i t ( m a s k o p t i o n ) m a s k o p t i o n o p
? 11 cxp85452/85460 * 1 v in and v out should not exceed v dd + 0.3v. * 2 the large current output port is port d (pd) and port f (pf). note) usage exceeding absolute maximum ratings may permanently impair the lsi. normal operation should better take place under the recommended operating conditions. exceeding those conditions may adversely affect the reliability of the lsi. supply voltage input voltage output voltage mid-voltage drive output voltage high level output current high level total output current low level output current low level total output current operating temperature storage temperature allowable power dissipation v dd v in v out v outp i oh i oh i ol i olc i ol topr tstg p d ?.3 to +7.0 ?.3 to +7.0 * 1 ?.3 to +7.0 * 1 ?.3 to +15.0 ? ?0 15 20 130 ?0 to +75 ?5 to +150 1000 600 v v v v ma ma ma ma ma c c mw mw pf0 to pf3 pins total of all output pins ports excluding large current output (value per pin) large current output port (value per pin) * 2 total of all output pins sdip qfp item symbol ratings unit remarks absolute maximum ratings (vss = 0v reference) supply voltage high level input voltage low level input voltage operating temperature 5.5 5.5 5.5 v dd v dd v dd + 0.3 0.3v dd 0.2v dd 0.4 +75 v v v v v v v v v c item symbol min. max. unit remarks 4.5 3.5 2.5 0.7v dd 0.8v dd v dd ?0.4 0 0 ?.3 ?0 v ih v ihs v ihex v il v ils v ilex topr guaranteed operation range for 1/2 and 1/4 frequency dividing modes. guaranteed operation range for 1/16 frequency dividing mode or sleep mode. guaranteed data hold range for stop mode. * 1 * 2 * 3 extal pin * 4 * 2 * 3 extal pin * 4 v dd * 1 this device does not enter the stop mode. * 2 pa, pb, pc, pe2 to pe5, scl0, scl1, sda0, sda1 pins * 3 int2, sck, si, hs0, hs1, rmc, ec, int0, int1, hsync, vsync, rst pins * 4 specifies only during external clock input. recommended operating conditions (vss = 0v reference)
? 12 cxp85452/85460 v dd = 4.5v, i oh = ?.5ma v dd = 4.5v, i oh = ?.2ma v dd = 4.5v, i ol = 1.8ma v dd = 4.5v, i ol = 3.6ma v dd = 4.5v, i ol = 3.0ma v dd = 4.5v, i ol = 4.0ma v dd = 5.5v, v ih = 5.5v v dd = 5.5v, v il = 0.4v v dd = 4.5v, i ol = 12.0ma high level output voltage low level output voltage input current i/o leakage current open drain output leakage current (n-ch tr off) i 2 c bus switch connection impedance (output tr off) supply current input capacitance 4.0 3.5 18 0.9 10 3 20 a pf 30 50 10 120 ma ma a a 0.4 0.6 1.5 0.4 0.6 40 ?0 ?00 10 v v v v v a a a a 0.5 ?.5 ?.5 v v pa to pd, pe6, pe7, r, g, b, i, ys, ym pa to pd, pe6, pe7, r, g, b, i, ys, ym, pf0 to pf3, rst * 1 pd, pf pf4 to pf7 (scl0, scl1, sda0, sda1) extal rst * 2 pa to pe, hsync, vsync, r, g, b, i, ys, ym, rst * 2 pf0 to pf3 pf4 to pf7 scl0: scl1 sda0: sda1 v dd = 5.5v, v il = 0.4v v dd = 5.5v, v i = 0, 5.5v v dd = 5.5v, v oh = 12.0v v dd = 5.5v, v oh = 5.5v v dd = 4.5v v scl0 = v scl1 = 2.25v v sda0 = v sda1 = 2.25v v dd * 3 1/2 frequency dividing operation mode v dd = 5.5v, 8mhz crystal oscillation (c 1 = c 2 = 22pf) stop mode * 4 v dd = 5.5v, termination of 8mhz oscillation sleep mode v dd = 5.5v, 8mhz crystal oscillation (c 1 = c 2 = 22pf) pa to pd, pe0 to pe5, scl, sda, exlc, extal, rst 1mhz clock 0v for non-measurement pins item symbol pin condition min. typ. max. unit v oh v ol i iz i loh r bs i dd i ddsl i ddst c in i ihe i ihl i ilr dc characteristics (ta = ?0 to +75 c, vss = 0v reference) * 1 specifies rst pin only when the power-on reset circuit is selected with mask option. * 2 for rst pin, specifies the input current when pull-up resistor is selected, and specifies the leakage current when non-resistor is selected. * 3 when all output pins open. specifies only when the osd oscillation is halted. * 4 this device does not enter the stop mode.
? 13 cxp85452/85460 ac characteristics (1) clock timing (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) fig. 1. clock timing e x t a l t x h t x l t c f t c r 0 . 4 v v d d 0 . 4 v 1 / f c fig. 2. clock applied condition a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a c r y s t a l o s c i l l a t i o n c e r a m i c o s c i l l a t i o n e x t a l x t a l e x t e r n a l c l o c k e x t a l x t a l o p e n c 1 c 2 fig. 3. event count clock timing e c t e h t e l t e f t e r 0 . 2 v d d 0 . 8 v d d * 1 t sys indicates three values according to the contents of the clock control register (clc: 00fe h ) upper 2 bits (cpu clock selection). t sys (ns) = 2000/fc (upper 2 bits = "00"), 4000/fc (upper 2 bits = "01"), 16000/fc (upper 2 bits = "11") system clock frequency system clock input pulse width system clock rise and fall times event count input clock pulse width event count input clock rise and fall times f c t xl , t xh t cr , t cf t eh , t el t er , t ef xtal extal extal extal ec ec mhz ns ns ns ms item symbol pin condition min. max. unit fig. 1, fig. 2 fig. 1, fig. 2 external clock drive fig 1, fig 2 external clock drive fig. 3 fig. 3 3.5 50 t sys + 50 * 1 9 200 20
? 14 cxp85452/85460 (2) serial transfer (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) fig. 4. serial transfer timing 0 . 2 v d d 0 . 8 v d d t k l t k h s o t k c y t s i k t k s i 0 . 2 v d d 0 . 8 v d d t k s o 0 . 2 v d d 0 . 8 v d d o u t p u t d a t a i n p u t d a t a s i s c k item sck cycle time t kcy sck input mode output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode 1000 8000/fc 400 4000/fc ?50 100 200 200 100 200 100 ns ns ns ns ns ns ns ns ns ns sck si si so t kh t kl t sik t ksi t kso sck high and low level widths si input set-up time (for sck - ) si hold time (for sck - ) sck ? so delay time symbol pin condition min. max. unit note) the load of sck output mode and so output delay time is 50pf + 1ttl.
? 15 cxp85452/85460 resolution linearity error zero transition voltage full-scale transition voltage conversion time sampling time analog input voltage v zt * 1 v ft * 2 t conv t samp v ian an0 to an3 ta = 25 c v dd = 5.0v vss = 0v ?0 4910 160/f adc * 3 12/f adc * 3 0 10 4970 8 3 70 5030 v dd bits lsb mv mv s s v item symbol pin condition min. typ. max. unit (3) a/d converter characteristics (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) l i n e a r i t y e r r o r v z t v f t a n a l o g i n p u t f f h f e h 0 1 h 0 0 h d i g i t a l c o n v e r s i o n v a l u e fig. 5. definitions for a/d converter terms * 1 v zt : digital conversion values change between 00 h ? ? 01 h . * 2 v ft : digital conversion values change between 0e h ? ? 0f h . * 3 f adc indicates the below values due to the contents of bit 6 (cks) of the a/d control registor (adc: 00f6 h ) and the bits 7 (pck1) and 6 (pck0) of the clock control registor (clc: 00fe h ) 00 ( f = f ex /2) 01 ( f = f ex /4) 11 ( f = f ex /16) f adc = f c /2 f adc = f c /4 f adc = f c /16 f adc = f c cks pck1, 0 0 ( f /2 selection) 1 ( f selection) f adc = f c /2 f adc = f c /8
? 16 cxp85452/85460 external interruption high and low level widths reset input low level width int0 to int2 rst 1 8/fc s s item symbol pin condition min. max. unit t ih t il t rsl power supply rise time power supply cutt-off time t r t off v dd power-on reset repeated power-on reset 0.05 1 50 ms ms item symbol pin condition min. max. unit (4) interruption, reset input (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) (5) power-on reset power-on reset * 1 (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) 0 . 2 v d d 0 . 8 v d d t i h t i l i n t 0 t o i n t 2 ( f a l l i n g e d g e ) * 1 specifies only when power-on reset function is selected. 0 . 2 v 0 . 2 v 4 . 5 v v d d t r t o f f t a k e c a r e w h e n t u r n i n g o n p o w e r . fig. 6. interruption input timing t r s l 0 . 2 v d d r s t fig. 7. rst input timing fig. 8. power-on reset
? 17 cxp85452/85460 (6) i 2 c bus timing (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) item scl clock frequency bus-free time before starting transfer hold time for starting transfer clock low level width clock high level width set-up time for repeated transfers data hold time data set-up time sda, scl rise time sda, scl fall time set-up time for transfer completion f slc t buf t hd; sta t low t high t su; sta t hd; dat t su; dat t r t f t su; sto scl sda, scl sda, scl scl scl sda, scl sda, scl sda, scl sda, scl sda, scl sda, scl 0 4.7 4.0 4.7 4.0 4.7 0 * 1 250 4.7 100 1 300 khz s s s s s s ns s ns s symbol pin condition min. max. unit * 1 for the data hold time, the scl rise time (300ns max.) is not considered so that 300ns should be exceeded. fig. 9. i 2 c bus transfer data timing p s t t s u ; s t o t s u ; s t a t h d ; s t a t s u ; d a t t h i g h t h d ; d a t t f t r t l o w t h d ; s t a s p t b u f s d a s c l fig. 10. i 2 c device recommended circuit i 2 c d e v i c e i 2 c d e v i c e r s r s r s r s r p r p s d a 0 ( o r s d a 1 ) s c l 0 ( o r s c l 1 ) a pull-up resistor (rp) must be connected to sda0 (or sda1), and scl0 (or scl1). the sda0 (or sda1) and scl0 (or scl1) series resistance (rs = 300 or less) can be used to reduce spike noise caused by crt flashover.
? 18 cxp85452/85460 (7) osd timing (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) item osd clock frequency hsync pulse width vsync pulse width hsync afterwrite rise and fall times vsync beforewrite rise and fall times f osc t hwd t vwd t hcg t vcg exlc xlc hsync hsync hsync vsync fig. 12 fig. 11 fig. 11 fig. 11 fig. 11 4 1.2 1 7 * 1 14 * 2 200 1.0 mhz s h * 3 ns s symbol pin condiiton unit min. max. * 1 oscillation clock at 4mhz operation * 2 oscillation clock at 8mhz operation * 3 h indicates 1hsync period. fig. 11. osd timing 0 . 8 v d d 0 . 2 v d d t h c g t h w d h s y n c f o r o s d i / o p o l a r i t y r e g i s t e r ( o p o l : 0 1 f a h ) b i t 7 a t 0 0 . 8 v d d 0 . 2 v d d t v c g v s y n c f o r o s d i / o p o l a r i t y r e g i s t e r ( o p o l : 0 1 f a h ) b i t 6 a t 0 t v w d fig. 12. lc oscillation circuit connection l c 2 c 1 e x l c x l c r * 1 * 1 the series resistor for xlc is used to reduce the frequency of occurrence of the undesired radiation.
? 19 cxp85452/85460 appendix fig. 13. spc700 series recommended oscillation circuit a a a a a a a a a a a a a a a e x t a l x t a l c 1 c 2 r d a a a a a a a a a a a a a a a e x t a l x t a l ( i ) a a a a a a a a a a a a a a a e x t a l x t a l c 1 c 2 r d x t a l ( i i ) manufacturer murata mfg co., ltd. kinseki ltd. model csa4.00mg csa4.19mg csa8.00mtz cst4.00mgw * 1 cst4.19mgw * 1 cst8.00mtw * 1 hc-49/u03 hc-49/u(-s) fc (mhz) 4.00 4.19 8.00 4.00 4.19 8.00 4.00 4.19 8.00 4.00 4.19 8.00 30 12 30 12 0 * 2 0 * 2 c 1 (pf) c 2 (pf) rd ( ) circuit example (i) (ii) (i) 27 27 0 * 2 (i) * 1 these models have the on-chip grounding capacitors (c 1 and c 2 ). * 2 the series resistor for xtal can reduce the effect of the noise caused by the electrostatic discharge. river eletec co., ltd. item inclusion reset pin pull-up resistor power-on reset circuit non-existent non-existent existent existent mask option table
? 20 cxp85452/85460 fig. 14. characteristics curves 2 3 1 4 5 6 0 . 1 1 0 1 5 1 0 8 6 4 2 0 1 1 6 1 4 1 2 1 2 1 4 1 0 0 1 0 0 l i n d u c t a n c e [ h ] p a r a m e t e r c u r v e f o r o s d o s c i l l a t o r l v s . c ( a n a l y t i c a l l y c a l c u l a t e d v a l u e ) 5 0 1 0 0 c 1 , c 2 c a p a c i t a n c e [ p f ] 5 . 0 m h z 6 . 5 m h z 1 3 . 0 m h z v d d s u p p l y v o l t a g e [ v ] i d d s u p p l y c u r r e n t [ m a ] i d d v s . v d d ( f c = 8 m h z , t a = 2 5 c , t y p i c a l ) f c s y s t e m c l o c k [ m h z ] i d d v s . f c ( v d d = 5 v , t a = 2 5 c , t y p i c a l ) f r e q u e n c y m o d e s l e e p m o d e f r e q u e n c y m o d e 1 1 6 f r e q u e n c y m o d e s l e e p m o d e 2 0 1 8 1 6 1 4 1 2 1 0 i d d s u p p l y c u r r e n t [ m a ] f o s c = c = c 1 / / c 2 1 2 p ? l c f r e q u e n c y m o d e f r e q u e n c y m o d e f r e q u e n c y m o d e
? 21 cxp85452/85460 package outline unit: mm p a c k a g e s t r u c t u r e m o l d i n g c o m p o u n d l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e w e i g h t s o n y c o d e e i a j c o d e j e d e c c o d e s d i p - 6 4 p - 0 1 4 2 a l l o y s o l d e r p l a t i n g e p o x y / p h e n o l r e s i n 6 4 p i n s d i p ( p l a s t i c ) 7 5 0 m i l s d i p 0 6 4 - p - 0 7 5 0 - a 5 7 . 6 0 . 1 + 0 . 4 6 4 3 3 1 3 2 1 . 7 7 8 1 9 . 0 5 1 7 . 1 0 . 1 + 0 . 3 0 t o 1 5 0 . 2 5 0 . 0 5 + 0 . 1 0 . 5 m i n 4 . 7 5 0 . 1 + 0 . 4 3 m i n 0 . 5 0 . 1 0 . 9 0 . 1 5 8 . 6 g s o n y c o d e e i a j c o d e j e d e c c o d e 2 3 . 9 0 . 4 2 0 . 0 0 . 1 1 . 0 0 . 4 0 . 1 + 0 . 1 5 1 4 . 0 0 . 1 1 1 9 2 0 3 2 3 3 5 1 5 2 6 4 0 . 1 5 0 . 0 5 + 0 . 1 2 . 7 5 0 . 1 5 1 6 . 3 0 . 1 0 . 0 5 + 0 . 2 0 . 8 0 . 2 m 0 . 1 2 0 . 1 5 + 0 . 4 1 7 . 9 0 . 4 + 0 . 4 + 0 . 3 5 6 4 p i n q f p ( p l a s t i c ) q f p 6 4 p l 0 1 * q f p 0 6 4 p 1 4 2 0 p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e w e i g h t e p o x y r e s i n s o l d e r / p a l l a d i u m c o p p e r / 4 2 a l l o y p a c k a g e s t r u c t u r e p l a t i n g 1 . 5 g

▲Up To Search▲

Price & Availability of CXP85452S

	To Download CXP85452S Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .